Reliability-Oriented Multi-Class Fault-Injection Acceleration for Digital Integrated Circuits via Heterogeneous Spatio-Temporal Graph Learning

Vollständiger Abstract

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The pre-silicon reliability analysis of digital integrated circuits relies on fault-injection campaigns to characterize how single-event upsets propagate into distinct system-level outcomes. Exhaustive gate-level injection is expensive, whereas most learning-based accelerators collapse failure manifestations into a single binary label, thereby providing limited support for reliability diagnosis and follow-up analysis. We present a reliability-oriented reduced-campaign framework that predicts the monitor-defined outcome type of flip-flop (FF)-level cases omitted from a fixed circuit/workload campaign. For each circuit, Cadence Xcelium first performs SA0/SA1 screening and retains an FF when at least one stuck-at polarity produces a monitored failure. Within the resulting transient campaign, FeatureCoverage selects FF–time cases using structural attributes and fault-free activity statistics without reading their transient-fault outcomes. HSTGNN then combines a 60-cycle FF logic-value window from the same fault-free waveform, netlist-derived FF–FF topology and gate-path attributes, and module hierarchy to predict five outcomes: C0 No Error, C1 Result Error, C2 Exception Error, C3 Timeout Error, and C4 Safety Error. On the I2C, SPI, FIFO, and RISC-V benchmarks, HSTGNN achieves an 81.2–99.0% macro F1 on more than 38,000 held-out FF–time cases under a 70% labeled fault-injection budget comprising 60% training and 10% validation cases. FeatureCoverage also yields the highest macro F1 across all four label-free split strategies in every evaluated circuit. The proposed framework predicts the remaining 30% of cases while preserving reliability-relevant outcome semantics that binary acceleration discards. The evidence is limited to within-campaign prediction and supports, rather than replaces, quantitative reliability and diagnostic-coverage analysis.