A Back-Gate Corner-Closure Methodology for All-Digital Multi-Modulus Dividers in 22 nm FDSOI

Vollständiger Abstract

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The first divider in the feedback path of a frequency synthesizer runs at the full oscillator frequency and so constrains the speed and the power of the loop. Current-mode logic reaches high speed but draws a constant bias current independent of switching activity, whereas an all-digital, fully static-CMOS divider draws only dynamic and leakage current at the cost of far greater timing sensitivity to process, voltage, and temperature (PVT) variation. This paper presents a wide-range all-digital multi-modulus divider in 22 nm fully depleted silicon-on-insulator (FDSOI) technology, together with the methodology that makes the digital approach robust. The chain exhibits three distinct PVT failure modes, setup at the slow corners, hold at the fast-cold corner, and collapse of the internal clock duty cycle at the skewed corners; each is identified analytically and closed by a scheme combining back-gate body bias, a per-stage programmable delay trim, and a systematic integral-nonlinearity trim. Characterization is by post-layout simulation over a 45-point corner matrix, with the applied back-gate rail voltages and trim codes reported for every point. The divider covers N= 8 to 127, reaches 39.5 GHz at the typical corner, and holds a worst-case 33.0 GHz across the corner box against a 33 GHz target that the uncompensated chain misses at the slow and skewed low-supply corners (SS, SF, and FS at 0.72 V). A paired Monte Carlo campaign of 100 samples with process and mismatch variation, run at the binding corner, raises the yield at the target from 39% uncompensated to 72% with a single global back-gate setting and 99% with a per-die setting. At the target the divider consumes 5.3 mW at N=127 (6.2 GHz/mW) with 35.2 fs of additive jitter in a 0.005 mm2 core. The bias and trim settings are chosen by an external search and applied as fixed per-corner values; the monitors, controller, and bias generator that an autonomous implementation would require are specified but not designed, so the work demonstrates externally calibrated corner closure rather than a self-contained compensation system.